In semiconductor device production steps, new metallic materials having a low resistance value (Cu, etc.) and low-dielectric constant (low-k) materials are coming to be employed as wiring and interlayer insulating film, respectively, in order to attain increases in speed and integration degree in the devices.
A substrate for semiconductor devices is produced by first forming deposit layers including a metal film and an interlayer insulating film on a silicon wafer substrate, subsequently subjecting the wafer substrate to chemical mechanical polishing (hereinafter referred to as “CMP”) to conduct surface planarization, and stacking new layers on the planarized surface. In the substrate for semiconductor devices, each layer must be highly precisely planar.
On the surface of the semiconductor device substrate which has undergone the CMP step, various foreign matters remain. For example, the foreign matters include dust particles resulting from the polishing of the metallic wiring or low-dielectric constant film, colloidal silica contained in the slurry used in the CMP step, and organic residues derived from the anticorrosive contained in the slurry. For producing a semiconductor device having a multilayer structure, it is essential to remove such foreign matters. However, there are problems such as the following. The low-dielectric constant film is difficult to clean because the low-dielectric constant film is hydrophobic, has a low affinity for water, and repels the cleaning liquid. Furthermore, the colloidal silica is as extremely small as 100 nm or below and hence is difficult to remove. Although the organic residues can be dissolved away or decomposed, use of a cleaning liquid which has high dissolving or decomposing ability corrodes of the metallic wiring. In order to overcome these problems, application of various cleaning techniques is being attempted.
A most important technique among these is to control zeta potential. It is known that in acidic water, the surface of a semiconductor device substrate into which copper wiring has been introduced is negatively charged. Meanwhile, it is known that the colloidal silica contained in the slurry which is in use in the CMP step is positively charged in acidic water. In the case where the cleaning liquid contains no anionic surfactant, the fine colloidal silica particles which have been positively charged are apt to adhere to the negatively charged surface of the semiconductor device substrate in the substrate cleaning step that is conducted subsequently to the CMP step. For preventing this adhesion, it is necessary to control the zeta potential of the colloidal silica so as to be negative.
In addition, the substrate cleaning step, which is conducted subsequently to the CMP step, is further required to be less apt to cause corrosion of the Cu wiring. Since the degree of integration in devices is becoming higher and the Cu wiring is becoming thinner especially in recent years, there are cases where even slight corrosion which was not problematic in conventional devices can be a cause of a decrease in yield.
In order to overcome such a problem, application of various cleaning techniques is being attempted.
For example, in patent document 1, a cleaning liquid obtained by adding an alkali or an organic acid to a specific surfactant and water is disclosed in order to remove fine particles and organic contaminants which have adhered to a substrate.
In patent document 2, a cleaning liquid which contains a nonionic surfactant, e.g., polyoxyethylene nonylphenyl ether, a compound that forms a complex with a metal, such as aminoacetic acid or quinaldinic acid and an alkali ingredient is disclosed.
In patent document 3, a cleaning liquid which contains only one carboxylic acid type anionic surfactant as the surfactant is disclosed.
In patent document 4, an alkaline cleaning liquid which contains a carboxylic acid type anionic surfactant is disclosed.